Dynamic data packet flow control for packet switching node

ABSTRACT

A data packet switching node that temporarily stores data packets received from at least one source network adapter and transmits them to at least one destination network adapter comprises a data packet flow control system to control the data packet flow. The data packet flow control system comprises identifier to determine the at least one destination adapter of each received data packet. Then, means coupled to the storage allow computing a data packet flow value representing the traffic for the at least one destination adapter. The data packet flow value is transmitted simultaneously to the at least one source network adapter and to the at least one destination network adapter each time a data packet for the at least one destination network adapter is stored into the storage.

TECHNICAL FIELD

[0001] The present invention relates to the flow control of data packetstransmitted between Local Area Networks (LAN) interconnected by a switchengine.

BACKGROUND ART

[0002] Local Area Networks (LAN) such as Ethernet or token-ringnetworks, are generally interconnected through hubs. The hub is a systemmade of LAN adapters that communicate together through a switch card.The switch card is mainly composed of input ports, output ports and ashared memory switch engine.

[0003] The data packets received by the input ports are stored into theshared memory at address locations determined by queues containing thepacket destination addresses. The packets are de-queued to betransmitted to the destination output ports.

[0004] The shared memory having a limited size, a flow control mechanismis generally implemented to control the data packet transfer betweeneach adapter card and the switch engine. Flow control mechanisms areoften based on thresholds. The shared memory has a maximum threshold anda minimum threshold. When the number of data packets stored into theshared memory reaches the max. threshold, the switch engine asks theadapter card to stop sending data packets. When the number of datapackets stored into the shared memory reaches the min threshold, theswitch engine asks the adapter card to resume the transmission of datapackets. Drawback of such mechanism is that it is a binary control whichoperates as ‘do transmit’ or ‘do not transmit’, thereby leading tointerrupt and resume the data flow.

[0005] Therefore, there is a need to have a flow control system whereinthe transmission from the adapter cards is never stopped. The presentinvention offers such solution.

SUMMARY OF THE INVENTION

[0006] Accordingly, it is an object of the invention to provide a smoothflow control mechanism between adapter cards and a switch engine.

[0007] It is another object to provide a flow control system having lesslatency between the adapter cards and the switch engine.

[0008] It is yet another object of the invention to offer an optimal useof the shared memory of the switch engine.

[0009] In a preferred embodiment, the invention relates to a datatransmission system comprising a plurality of Local Area Networks (LANs)interconnected by several hubs. Each hub contains a Control Point card,a plurality of adapter cards connected to the Local Area Networks and aswitching system made of two switch cards, one being active and theother being backup.

[0010] Each data packet transmitted by any adapter card to the switchengine includes a header containing at least the address of the adaptercard to which the data packet is forwarded.

[0011] The system of the invention operates both in the switch engineand the adapter cards. It comprises a flow control circuitry associatedto the shared memory where the data packets are stored. The flow controlcircuitry operates between each adapter card and the active switch card.

[0012] In a preferred embodiment, a data packet switching node thattemporarily stores data packets received from at least one sourcenetwork adapter and transmits them to at least one destination networkadapter comprises a data packet flow control system to control the datapacket flow. The data packet flow control system is characterized inthat it comprises:

[0013] identifier means to determine the at least one destinationadapter of each received data packet;

[0014] means coupled to the storing means for computing a data packetflow value representing the traffic for the at least one destinationadapter; and

[0015] means coupled to the identifier means and to the computing meansfor transmitting the computed data packet flow value simultaneously tothe at least one source network adapter and to the at least onedestination network adapter each time a data packet for the at least onedestination network adapter is stored into the storing means.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of theinvention will be better understood by reading the following moreparticular description of the invention in conjunction with theaccompanying drawings wherein:

[0017]FIG. 1 is a schematic diagram of a data transmission systemincluding four LANs interconnected by a hub according to the principlesof the invention;

[0018]FIG. 2 is a schematic diagram of the switch card of FIG. 1;

[0019]FIG. 3 details the Lease Address Selector block of FIG. 2;

[0020]FIG. 4 details the Release Address Selector block of FIG. 2;

[0021]FIG. 5 details the Flow Control Logic of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] The invention is preferably implemented in a data transmissionenvironment as illustrated on FIG. 1. For sake of simplicity, theenvironment is made of four Local Area Networks (LAN) 10_1, 10_2, 10_3,and 10_4 but it could be extended to a plurality of LANs and as such aLAN is also denoted 10_i in the description. LANs 10-i areinterconnected together by a hub 12, and may be of the type ATM,Ethernet, or token-ring. Each LAN is connected to a switching system 14within the hub 12 by means of a respective adapter card 16_1 for LAN10_1, adapter card 16_2 for LAN 10_2, adapter card 16_3 for LAN 10_3 andadapter card 16_4 for LAN 10_4. Each adapter card (also denoted 16_i)sends data packets by means of a data bus-in (bus-in 13_1 to bus-in13_4) connected to input ports of the switching system 14. Each adaptercard receives data packets by means of a data bus-out (bus-out 15_1 tobus-out 15_4) connected to output ports of the switching system 14.Then, a data bus-in 13_i carries data packets from the respectiveadapter card 16_i to switching system 14 and data bus-out (15_i) carriesdata packets from switching system 14 to the adapter card 16_i. Eachadapter card also receives flow control information from the switchingsystem 14 by means of a serial interface 17. Then, a serial signal 17carries flow control information from the switching system 14 to therespective adapter card 16_i. The switching system 14 is made of twodistinct switch cards, an active switch card 14_1 and a backup switchcard 14_2. The invention is located within each switch card but for theease of description, let's only describe the active switch card 14_1.

[0023] Referring now to FIG. 2, the invention is described as part ofthe switch card 14_1. For the ease of comprehension, let's describe thetransmission of a data packet from adapter card 16_1 on data bus-in 13_1to adapter card 16_2 on data bus-out 15_2. It is to be easily understoodthat adapter cards 16_1 and 16_2 are only taken as example. In thepreferred embodiment, the switch card is mainly composed of:

[0024] a Shared Memory 250;

[0025] a Header Detection and Packet Validation block 100_1;

[0026] a Memory Write entity made of:

[0027] an En-queue Register block 380_1,

[0028] a Lease Address Selector block 350,

[0029] a Memory Write Controller block 150;

[0030] a Memory Read entity made of:

[0031] a De-queue Destination FIFO block 310_2,

[0032] a Release Address Selector block 300,

[0033] a Memory Read Controller block 200,

[0034] a Destination Output Buffer block 280_2;

[0035] a Free Buffer Queue block 400;

[0036] a Flow Control block 450.

[0037] The structure and operation of the different blocks are nowdescribed.

[0038] Shared Memory (250)

[0039] The Shared Memory receives data packets from adapter card 16_1 ondata bus-in 13_1 and transmits them to adapter card 16_2 on data bus-out15_2 through the Destination Output Buffer block 280_2. The writeoperation is controlled by bus 160 and the read operation by bus 210.

[0040] Header Detection and Packet Validation (100_1):

[0041] Generally, a data packet is made of a header and a payload. Theheader contains information such as a destination address, a prioritylevel, and the payload contains the data.

[0042] The Header Detection and Packet Validation block 100_1 receivesdata packets from adapter card 16_1 through data bus-in 13_1. When avalid data packet is detected the destination address is extracted andgenerated on bus 140_1. In addition, a write enable signal 130_1 isactivated.

[0043] Memory Write Entity:

[0044] The Memory Write Entity is made of an En-queue Register block380_1, a Lease Address Selector block 350 and a Memory Write Controllerblock 150.

[0045] To detail more each task:

[0046] The En-queue Priority Register block 380_1 contains the addresswhere to store an incoming data packet. The address comes from the FreeBuffer Queue block 400 through bus 410. The output bus 370_1 isconnected to the Lease Address Selector block 350.

[0047] The Lease Address Selector block 350 for destination adapter 16_2is illustrated in FIG. 3. Its function is to transfer the address storedinto En-queue Register block 380_1 onto bus 360 through the buffer block351. The destination address of the incoming data packet is received onbus 140 by the Destination Decoder block 330 which decodes and activatesthe corresponding destination chip select signal 360_2. This chip selectsignal is carried out to Flow Control block 450 and to the De-queueDestination write FIFO input.

[0048] The Memory Write Controller block 150 controls the Shared Memoryblock 250 through bus 160. The write address comes from bus 360 and thewrite command comes from signal 130_1.

[0049] Memory Read Entity:

[0050] The Memory Read Entity is made of a De-queue FIFO block 310_2, aRelease Address Selector block 300 and a Memory Read Controller block200.

[0051] To detail more each task:

[0052] The De-queue Destination FIFO block 310_2 contains the addressesof incoming data packets that have been stored for a transmission toadapter 16_2. The input interface is made of an input FIFO data busconnected to the address bus 360 and an input FIFO write signalconnected to the destination chip select signal 360_2. The outputinterface is made of an output FIFO data bus 320 and an input FIFO readsignal 320_2, both being connected to the Release Address Selector block300.

[0053] The Release Address Selector block 300 for destination adapter16_2 is illustrated in FIG. 4. Its function is to de-queue and releasememory read addresses. A State Machine 301 controls the address de-queuein a round-robin fashion from adapter 16_1 to adapter 16_4. For sake ofsimplicity, only destination adapter 16_2 is described. A Comparatorblock 330_2 and a Buffer block 340_2 are connected to the output FIFOdata bus 320. The output bus of the buffer is connected to the MemoryRead Controller block 200 through bus 220. The State Machine 301receives the output control signal of Comparator block 330_2 on signal301_2 and generates a De-queue Destination read FIFO signal 320_2 and amemory read signal 270_2. The read signal is connected to the MemoryRead Controller block 200, the Destination Output Buffer block 280_2 andthe Flow Control block 450. The State Machine 301 is clocked by theoutgoing data packet clock received on signal 301_5. The Release AddressSelector block 300 performs the following tasks:

[0054] reads the De-queue Destination FIFO of adapter 16_2 by activatingsignal 320_2,

[0055] compares its content to zero which is the default value when theFIFO is empty,

[0056] if the control signal 301_2 is activated, performs a memory readoperation and release the address into the Free Buffer Queue block 400;if the control signal 301_2 is not activated reads the De-queueDestination FIFO of next adapter.

[0057] The Memory Read Controller block 200 controls the Shared Memoryblock 250 through bus 210. The read address comes from bus 220 and theread command comes from signal 270_2. The data packet is transmittedfrom the memory to adapter 16_2 through the Destination Output Bufferblock 280_2 on bus 15_2.

[0058] Free Buffer Oueue block (400):

[0059] The Free Buffer Queue block 400 contains memory addresses readyto be used. Its output bus 410 provides addresses to the En-queueRegister for memory write operations. Its input bus 220 receivesaddresses from the Release Address Selector block 300 when a memory readoperation has been completed.

[0060] Referring now to FIG. 5, the Flow Control block 450 fordestination adapter 16_2 is mainly composed of:

[0061] a Microprocessor Interface block 25;

[0062] a flow control logic per adapter made of:

[0063] a Threshold Register block 31_2,

[0064] a Counter/De counter block 41_2,

[0065] a Substract Logic block 51_2

[0066] an ID register block 61_2;

[0067] a Serializer block 70.

[0068] The structure and operating of the different blocks are nowdescribed.

[0069] Microprocessor Interface (25):

[0070] The microprocessor interface block 25 is connected to the ControlPoint card 21 through bus 20. The interface allows the user to accessthe Threshold register block 31_2 in order to predefined a thresholdvalue.

[0071] Flow Control Logic:

[0072] It is made of a Threshold register block 31_2, a Counter/Decounter block 41_2, a Substract logic block 51_2 and an ID registerblock 61_2.

[0073] To detail more each task:

[0074] a. The Threshold register is programmed through themicroprocessor interface by the user which access the Control Pointcard. Its output bus 32_2 is connected to a first port ‘A’ of theSubstract logic block 51_2.

[0075] b. The Counter block is incremented each time a data packet isstored into the shared memory 250 and is decremented each time a datapacket is read from the shared memory. An increment input signal isconnected to the Lease Address Selector block 350 through signal 360_2.A decrement input signal is connected to the Release Address Selectorblock 300 through signal 270_2. The Counter/De counter data bus 42_2 isconnected to a second port ‘B’ of the Substract logic block 51_2.

[0076] c. The Substract combinatorial logic block 51_2 always computeson the fly the difference between the two input ports ‘A-B’. The resultis only transmitted to serializer 70 onto bus 71 when signal 270_2 isactivated which means each time a data packet for adapter 16_2 is storedinto shared memory 250. The result represents the flow controlinformation to be transmitted to the adapter cards. When the result isclose to the predefined threshold value, this means that the traffic tothe respective adapter is very low; when the result is close to zero,this means that the traffic to the respective adapter is heavy. Theresult is sent to all the adapters connected to the switch and when theflow control information is received by each adapter, each one may takeappropriate action to adapt its traffic. As an example let's assume thatthere is no traffic at all in the switch and therefore the shared memoryblock 250 stores and transmits the data packets only to adapter 16_2. Inthis case the counter/de counter is equal to zero and each adapterreceives the threshold value as the flow control information for adapter16_2. This means that adapter 16_2 is receiving data packets without anycongestion. Now, let's assume that there is a high priority trafficgoing on in the switch with adapter 16_3. The counter block 41_2 isincremented each time a data packet is stored for adapter 16_2 but willnot be decremented until the traffic for adapter 16_3 reduces. Thereforeeach adapter receives from the Substract logic a flow controlinformation going to zero. This means that adapter 16_2 is not receivingdata packets already sent. Therefore all adapters that want to transmitdata packets to adapter 16_2 should reduce their traffic until the flowcontrol information reaches again the threshold value. To recall, thepresent system allows a dynamic picture of the use of the shared memoryof the switch engine and provides a real time information to the wholeadapter cards communicating with the switch engine.

[0077] ID Register (61_2):

[0078] The ID Register block 61_2 provides the address of thedestination adapter. In a preferred embodiment, this address ishardwired on the board on 2 bits. As an alternative, the address shouldbe programmed from the Control Point through the microprocessorinterface.

[0079] Serializer (70):

[0080] The serializer block 70 receives a parallel bus 71 made of 10bits, 8 flow control bits which come from the substract logic block 51_2and 2 ID bits which come from the ID Register block 61_2. Each readaccess to the shared memory block 250 for adapter 16_2 activates thecontrol signal 270_2 which then starts the serializer. The transmissionbegins with the ID bits followed by the flow control bits. Thisinformation is received by each adapter card in the hub through theserial link 17.

[0081] The principle of operation of the system is now detailed aspreviously explained with adapter 16_1 transmitting a data packet toadapter 16_2. Adapter 16_1 first builds in a conventional manner a datapacket and sends it to the switch card 14 onto data bus-in 13_1. Next,the data packet is routed by the switch card using the routing indexinformation contained in its header. Then the data packet is transmittedto the destination adapter 16_2 on data bus-out 15_2. In parallel withthe transmission of the data packet, the flow control information issent to all the adapters 16_i through corresponding serial links 17.

[0082] The incoming data packet is analyzed by the Header Detection andPacket Validation block 100_1 which performs the following tasks:

[0083] sending the data packet destination address (port #2 in thedescription) to the Lease Address Selector block 350 through bus 140;

[0084] informing the Write Memory Controller block 150 through signal130_1 to perform a write operation.

[0085] Next the Lease Address Selector block 350 performs the followingtasks:

[0086] decoding the data packet destination address and activating thecorresponding chip select signal 360_2;

[0087] enabling the buffer block 351 to transmit the address stored intothe En-queue Register block 380_1 to the Write Memory Controller block150. This address was previously taken from the Free Buffer Queue block400;

[0088] storing this address into De-queue Destination FIFO block 310_2;

[0089] transferring the active chip select signal 360_2 to the FlowControl block 450 to increment counter block 41_2.

[0090] Finally the Write Memory Controller block 150 stores the datapacket into the Shared Memory block 250.

[0091] As a background task, the Release Address Selector block 300performs the following operations:

[0092] reading the De-queue Destination FIFO of adapter 16_2 byactivating signal 320_2;

[0093] comparing its content to zero which is the default value when theFIFO is empty;

[0094] if the control signal 301_2 is not activated, reading theDe-queue Destination FIFO of next adapter;

[0095] if the control signal 301_2 is activated, performing a memoryread operation and releasing the address into the Free Buffer Queueblock 400 for further use.

[0096] The Read Memory Controller block 200 controls the Shared Memoryblock 250 through bus 210. The read address comes from bus 220 and theread command comes from signal 270_2. The data packet is transmittedfrom the memory to adapter 16_2 through the Destination Output Bufferblock 280_2 on bus 15_2.

[0097] While the data packet is transmitted to adapter 16_2 the FlowControl block 450 transmits the flow control information to all adapterson serial link 17.

[0098] The counter is incremented when a data packet is stored into theshared memory 250 and decremented when a data packet is read. Thecontent of the counter/de counter is subtracted to the threshold valuedefined by the user at the initialization time. The result representsthe flow control information: when the value is close to the thresholdvalue the traffic to the adapter 16_2 is very low, when the value isclose to zero the traffic to the adapter 16_2 is heavy. This value alongwith the destination adapter address are serialized by Serializer block70 and send to each adapter card in the hub.

1. A data packet flow control system for a data packet switching nodethat transmits data packets received from at least one source networkadapter to at least one destination network adapter, the switching nodecomprising means for temporarily storing the data packets, the flowcontrol system comprising: identifier means (100-1) to determine the atleast one destination adapter of each received data packet; means (41-2,31-2, 51-2) coupled to the storing means for computing a data packetflow value representing the traffic for the at least one destinationadapter; and means (61-2, 70) coupled to the identifier means and to thecomputing means for transmitting the computed data packet flow valuesimultaneously to the at least one source network adapter and to the atleast one destination network adapter each time a data packet for the atleast one destination network adapter is stored into the storing means.2. The system of claim 1 wherein the means for computing a data packetflow value comprises: means (41-2) for counting every access to thestoring means; and means (31-2, 51-2) for comparing the counting to athreshold value.
 3. The system of claim 2 wherein the counting means isa counter incremented on each write access and decremented on each readaccess of the storing means.
 4. The system of claims 1 or 2 furthercomprising means (21, 25) to predefined the threshold value.
 5. Thesystem of anyone of claims 1 or 2 wherein each received data packetcomprises a header having at least a destination adapter address fieldand wherein the identifier means comprise means (100-1) for extractingthe destination adapter address from the destination adapter addressfield.
 6. The system of claims 1 or 2 wherein the storing meanscomprises means for setting active a write control signal at each writeaccess and means for setting active a read control signal at each readaccess.
 7. The system of claim 6 wherein the counter is incremented whenthe write control signal is active and is decremented when the readcontrol signal is active.
 8. The system of claim 1 wherein the at leastone source network adapter and the at least one destination networkadapter further comprise means to regulate the data packet flow uponreception of the data packet flow control value.
 9. The system of claim1 wherein the incoming data packets are ATM data packets.
 10. A datatransmission system comprising a plurality of Local Area Networks (LANs)(10-1 to 10-4) interconnected by a hub (12) including the same pluralityof LAN adapters (16-1 to 16-4) respectively connected to said LANs and adata packet switching node (14) interconnecting all LAN adapters totransmit a plurality of data packets from at least one source adapter ofthe plurality of LAN adapters to at least one destination adapter of theplurality of LAN adapters, each data packet including a headercontaining at least the address of the at least one destination adapterand wherein the data packet switching node comprises storing means tostore the plurality of incoming data packets, the data transmissionsystem being characterized in that the data packet switching nodecomprises a data packet flow control system according to claim
 1. 11.The data transmission system of claim 10 wherein the data packetswitching node comprises an active and a backup data packet flow controlsystem.